MIPS architecture

MIPS architecture - Wikipedia, the free encyclopedia: "MIPS architecture

MIPS Designer MIPS Computer Systems
Bits 64-bit (32→64)
Introduced 1981
Design RISC
Type Register-Register
Encoding Fixed
Branching Condition register
Endianness Bi
Extensions MDMX, MIPS-3D
Registers
32

* 31 32-bit GPRs (R0=0)
* 32 32-bit FP regs (paired DP)
* MIPS III has 32 64-bit GPRs and FPRs

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computing (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems (now MIPS Technologies). The early MIPS architectures were 32-bit, while later versions were 64-bit. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations).[1][2] MIPS32 and MIPS64 define a control register set as well as the instruction set."